Job Summary:
We are looking for a Senior FPGA Engineer with experience in porting ASIC designs to FPGA,
preferably using Xilinx FPGAs. The ideal candidate should have extensive experience in FPGA
design, timing closure, and Xilinx toolchains. Knowledge of Synplify is a plus.
Key Responsibilities:
• Port ASIC designs to Xilinx FPGA platforms, ensuring performance and area efficiency.
• Develop and optimize RTL (Verilog/VHDL) to meet FPGA design constraints.
• Perform timing closure, static timing analysis (STA), and floorplanning.
• Utilize Xilinx FPGA tool flow (Vivado) for synthesis, implementation, and bitstream
generation.
• Debug and validate FPGA implementations using simulation, hardware testing, and
debugging tools (e.g., Chipscope, SignalTap).
• Optimize FPGA performance through placement, routing, and power optimizations.
• Collaborate with ASIC and system engineers to ensure seamless integration.
• Experience with Synplify for synthesis is a plus.
• Proficiency in scripting languages (Tcl, Python, Perl) for automation is a plus.
Required Qualifications:
• Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field
• 3 to 12+ years of FPGA development experience.
• Expertise in Xilinx FPGAs, Verilog/VHDL, and FPGA debugging tools.
• Strong understanding of timing closure, STA, and FPGA optimization techniques.
Preferred Qualifications:
• Experience with Synplify for FPGA synthesis.
• Familiarity with ASIC-to-FPGA design migration.
• Knowledge of automation and scripting (Tcl, Python, Perl).